Low-temperature selective epitaxial growth of silicon for device integration

ABSTRACT

An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.

BACKGROUND

Technical Field

The present invention relates to semiconductor processing and moreparticularly to a low temperature epitaxial growth process.

Description of the Related Art

Selective epitaxial growth (SEG) of highly doped silicon is suitable forapplications in raised source/drain (S/D) regions to reduce parasiticseries resistance associated with shallow-doped S/D regions. However,conventional methods for SEG of silicon require high temperatureprocessing. The typical processing temperatures are greater than 600° C.

The high temperature requirement limits the processes and applicationswhich can utilize the conventional methods for SEG of Si. Further,conventional high temperature depositions (over 600 degrees C.) forepitaxial growth of silicon lack selective growth of Si on predeterminedareas, e.g., where the c-Si is exposed.

SUMMARY

An epitaxy method includes providing an exposed crystalline region of asubstrate material. Silicon is epitaxially deposited on the substratematerial in a low temperature process wherein a deposition temperatureis less than 500 degrees Celsius. A source gas is diluted with adilution gas with a gas ratio of dilution gas to source gas of less than1000.

Another epitaxy method includes providing a crystalline substratematerial; growing an insulator on the substrate material; opening theinsulator to form exposed areas of the substrate material; depositingsilicon on the exposed areas of the substrate material to form epitaxialsilicon on the exposed areas and form non-epitaxial silicon in otherthan the exposed areas in a low temperature process wherein a depositiontemperature is less than 500 degrees Celsius; and etching thenon-epitaxial silicon using a plasma to further epitaxial deposition ofsilicon over the exposed areas.

Yet another epitaxy method includes providing an exposed crystallineregion of a substrate material and epitaxially depositing siliconselectively on the substrate material in a low temperature processwherein a deposition temperature is less than 500 degrees Celsius, bydiluting a silane with a H₂ with a gas ratio of dilution gas to sourcegas of less than 1000.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of an illustrative semiconductor devicewith raised source/drain regions formed with selective epitaxial growthin accordance with one embodiment;

FIG. 2A is a diagram showing sheet resistance versus gas ratio for[PH₃]/[SiH₄] showing three illustrative samples in accordance with oneembodiment;

FIG. 2B is a diagram showing atom concentration versus depth for thethree samples of FIG. 2A and further showing a linear relationshipbetween P concentration and PH₃ flow in accordance with one example;

FIG. 3A is a cross-sectional view of a device having a selectiveepitaxial layer formed along with a non-epitaxial layer in a lowtemperature process in accordance with one embodiment;

FIG. 3B is a cross-sectional view of the device in FIG. 3A having thenon-epitaxial layer etched to further form the selective epitaxial layerin accordance with one embodiment;

FIG. 3C is a cross-sectional view of the device in FIG. 3B after thenon-epitaxial layer has been completely etched in accordance with oneembodiment;

FIG. 4 is a block/flow diagram showing an illustrative method forselective epitaxial growth in accordance with the present principles;and

FIG. 5 is a block/flow diagram showing another illustrative method forselective epitaxial growth using etching in accordance with the presentprinciples.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In accordance with the present principles, methods for selectiveepitaxial growth of highly-doped silicon at low temperatures aredisclosed. In particularly useful embodiments, growth temperatures aslow as 150° C. are achieved using plasma enhanced chemical vapordeposition (PECVD). The epitaxial growth is obtained by increasing andoptimizing a gas ratio of [H₂]/[SiH₄]. In another embodiment, an N⁺doped silicon is grown by, e.g., incorporating phosphorus using PH₃ gas.

High dopant activation, e.g., greater than 1×10²⁰ cm⁻³, can be obtainedat 150° C. Selective growth is provided by etching a deposited siliconon regions where crystalline-Si (c-Si) is not exposed, in H₂ plasma. Asa result, the present embodiments offer an uninterrupted selectiveepitaxial growth (SEG) of Si, where the epitaxial growth and the plasmaetching of the non-epitaxial Si occur in a same reactor. Selectiveepitaxial growth of boron doped Si or other dopants is also possibleusing the present methods.

The low temperature process in accordance with the present principlesopens up possibilities for many applications such as three-dimensional(3D) integration of devices, raised source/drain (S/D) regions fortransistors fabricated on extremely thin semiconductor on insulator(ETSOI), partially-depleted SOI (PDSOI), bulk silicon substrates, etc.and other applications.

Plasma enhanced chemical vapor deposition (PECVD) may also be employedfor low-temperature deposition of amorphous, microcrystalline,polycrystalline as well as epitaxial growth of silicon on a c-Sisubstrate at temperatures below 300° C.

The flowchart and diagrams in the Figures illustrate the architecture,functionality, and operation of possible implementations of variousembodiments of the present invention. It should also be noted that, insome alternative implementations, the functions noted in the blocks mayoccur out of the order noted in the figures. For example, two blocksshown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustrations,and combinations of blocks in the block diagrams and/or flowchartillustrations, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and instructions.

It is to be understood that the present invention will be described interms of a given illustrative architecture using silicon; however, otherarchitectures, structures, substrate materials and process features andsteps may be varied within the scope of the present invention.

Devices described herein may be part of a design for an integratedcircuit chip. The chip design may be created in a graphical computerprogramming language, and stored in a computer storage medium (such as adisk, tape, physical hard drive, or virtual hard drive such as in astorage access network). If the designer does not fabricate chips or thephotolithographic masks used to fabricate chips, the designer maytransmit the resulting design by physical means (e.g., by providing acopy of the storage medium storing the design) or electronically (e.g.,through the Internet) to such entities, directly or indirectly. Thestored design is then converted into the appropriate format (e.g.,GDSII) for the fabrication of photolithographic masks, which typicallyinclude multiple copies of the chip design in question that are to beformed on a wafer. The photolithographic masks are utilized to defineareas of the wafer (and/or the layers thereon) to be etched or otherwiseprocessed.

The methods as described herein may be used in the fabrication ofintegrated circuit chips. The resulting integrated circuit chips can bedistributed by the fabricator in raw wafer form (that is, as a singlewafer that has multiple unpackaged chips), as a bare die, or in apackaged form. In the latter case, the chip is mounted in a single chippackage (such as a plastic carrier, with leads that are affixed to amotherboard or other higher level carrier) or in a multichip package(such as a ceramic carrier that has either or both surfaceinterconnections or buried interconnections). In any case, the chip isthen integrated with other chips, discrete circuit elements, and/orother signal processing devices as part of either (a) an intermediateproduct, such as a motherboard, or (b) an end product. The end productcan be any product that includes integrated circuit chips, ranging fromtoys and other low-end applications to advanced computer products havinga display, a keyboard or other input device, and a central processor.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a device or wafer 100includes a substrate 102 wherein methods in accordance with the presentprinciples will be applied. Substrate 102 may include, e.g., a bulkmonocrystalline silicon substrate, a semiconductor-on-insulator (SOI),an extremely thin SOI (ETSOI) substrate, a partially-depleted SOI(PDSOI) substrate or other substrates. Other substrates may include Ge,III-V substrates (e.g., GaAs), etc. In the present embodiment, siliconis a preferred substrate material for epitaxial growth; however, othercrystalline substrate materials may also be employed in accordance withthe present principles.

The device 100 may be employed in three-dimensional (3D) integrationapplications or other applications where epitaxial growth is needed toform component layers. In a particularly useful embodiment, theepitaxial growth is employed to form raised source/drain (S/D) regionsfor transistors. The present embodiment will illustratively describeforming raised S/D regions although the present principles apply to anyepitaxial growth and etching applications.

A gate structure 106 is formed including a gate insulator 108 (e.g., anoxide), a gate conductor 110 (e.g., doped polysilicon), and spacers 112(e.g., nitride). Other gate structures and materials may also beemployed. FIG. 1 illustratively shows faceted S/D regions 120, althoughthe S/D regions 120 need not be faceted. S/D regions 120 are formed byepitaxial growth. The epitaxial growth may include a highly doped orundoped silicon at temperatures as low as 150 degrees C. onpredetermined areas of the substrate 102. This is preferably wherecrystalline silicon (c-Si) is exposed, hence selective epitaxial growth.

In one embodiment, the selective epitaxial growth of silicon isperformed in a hydrogen diluted silane environment using a plasmaenhanced chemical vapor deposition process (PECVD). The gas ratio ofhydrogen gas to silane gas ([H₂]/[SiH₄]) at 150 degrees C. is preferablybetween 0 to about 1000. In particularly useful embodiments, epitaxiallygrowth of silicon begins at a gas ratio of about 5-10. The epitaxial Siquality is improved by increasing the hydrogen dilution, e.g., to 5 orgreater.

Epitaxial silicon can be grown using various gas sources, e.g., silane(SiH₄), dichlorosilane (DCS), SiF₄, SiCl₄ or the like. The quality ofepitaxial silicon improves by increasing the dilution of hydrogen usingthese or other gases. For higher hydrogen dilution, smoother interfaceswere produced (epitaxial silicon to crystalline silicon) and fewerstacking faults and other defects were observed.

Radio-frequency (RF) or direct current (DC) plasma enhanced chemicalvapor deposition (CVD) is preferably performed at deposition temperatureranges from about room temperature to about 500 degrees C., andpreferably from about 150 degrees C. to about 250 degrees C. Plasmapower density may range from about 2 mW/cm² to about 2000 mW/cm². Adeposition pressure range may be from about 10 mtorr to about 5 torr.

In one embodiment, high dopant activation can be obtained attemperatures as low as 150 degrees C. This makes the present methodsattractive for applications in 3D integration and raised S/Dfabrications. The epitaxial Si may contain, e.g., carbon, germanium,phosphorus, arsenic, boron, etc. The low-temperature epitaxial Si may begrown on different substrates, such as Si, Ge, and III-Vs. For example,an epitaxial silicon layer was grown by the present inventors on GaAs atabout 200 degrees Celsius in accordance with the present principles.

Referring to FIG. 2A, sheet resistivity of phosphorus doped epitaxialsilicon (epi-Si) for various PH₃ gas flows is shown. Sheet resistivityfor ˜40-50 nm thick epi-Si doped for various PH₃ gas flows indicates ahigh dopant activation in silicon. The hydrogen to silane gas ratio was14. Secondary ion mass spectroscopy (SIMS) was carried out for thesamples denoted as 1, 2, and 3.

FIG. 2B shows P concentration (atoms/cm³) versus depth (nm) for samples1, 2 and 3. The P concentration is linearly proportional with PH₃ (seeinset 210). A corresponding level of the electrically active dopantsfrom the sheet resistivity measurements for the samples 1 and 2 is inagreement with the actual concentration of dopants given by the SIMSdata. The concentration of the electrically active dopants for thesample 3, however, is much lower than the total incorporated dopants,evident from the SIMS analysis of FIG. 2B. The epitaxial growth ofsilicon was disrupted by increasing the [PH₃]/[SiH₄] for sample 3, and anon-epitaxial phase of silicon began to grow. Similar results wereobtained for Boron incorporation. It should be understood that thedopant gas concentration should be maintained below a threshold gasratio to avoid a non-crystalline silicon phase or to provide anon-epitaxial phase, if desired. With respect to FIG. 2B, the thresholdappears to be at about a gas ratio of [PH₃]/[SiH₄] between about 5-8.Other gases/dopant processes have other thresholds.

Referring to FIGS. 3A-3C, in another embodiment, selective growth ofepitaxial silicon 302 on predetermined areas of a substrate 304 may beobtained by in-situ etching of non-epitaxial silicon in H₂ plasma 308.An etching process of amorphous silicon is employed to concurrently formepitaxial silicon on exposed crystalline silicon areas. It should beunderstood that the epitaxial growth and etching may be performedsequentially or concurrently as needed. In FIG. 3A, a window 312 isopened up within an insulator (e.g., silicon oxide (SiO₂)) layer 306,which is formed on substrate 304. Silicon 302 is deposited at, e.g., 500mTorr, [H₂]/[SiH₄]=14 and power density of 4 mW/cm². As a result, thesilicon 302 is epitaxial within the window areas 312 where the silicon302 is exposed to c-Si of the substrate 304. The silicon on theinsulator (e.g., oxide) 306 forms as non-epitaxial (e.g., amorphous)silicon 310.

In FIG. 3B, a H₂ plasma etch 308 is performed at 150 degrees C. at 900mtorr, resulting in an etch selectivity of approximately 1:3 for c-Si304 with respect to a-Si:H 310. FIG. 3C shows the selective epitaxialsilicon 302 and the non-epitaxial (amorphous in this case) Si 310removed. It should be understood that a non-epitaxial portion (amorphousSi 310) grown on the insulator 306 can be etched using gases such as,e.g., H₂, HCl, Cl₂, Ar, etc. The epitaxial deposition and the H₂ plasmaetch may be performed sequentially or concurrently in a same chamber.The selective epitaxial growth can be achieved either by alternating gaspulses responsible for the epitaxial growth (e.g., silane and dopantspecies) and the etch (plasma etchants, e.g., H₂, HCl, etc.) or bysimultaneous flow of all the gases.

Referring to FIG. 4, a method for selective epitaxial growth isillustratively shown. In block 402, an exposed crystalline region of asubstrate material is provided. This may include opening up windows in adielectric layer or patterning a layer on the substrate. The substratematerial may include Si, Ge, III-V materials, etc.

In block 404, silicon is epitaxially deposited on the substrate materialin a low temperature process wherein a deposition temperature is lessthan 500 degrees Celsius, and preferably less than 250 degrees Celsius.The process is selective to exposed areas of the substrate. The processpreferably includes a radio frequency or direct current plasma enhancedchemical vapor deposition process.

In block 408, a source gas is diluted with a dilution gas including atleast one of H₂, HCl, Cl₂ and Ar with a gas ratio of dilution gas tosource gas of less than 1000. The source gas may include one of SiH₄,dichlorosilane (DCS), SiF₄ or SiCl₄. In a particular useful embodiment,SiH₄ is employed with H₂ with a gas ratio [H₂]/[SiH₄] of over 5.

In block 410, a dopant species or multiple dopant species may beintroduced with a gas ratio which provides a doped epitaxial silicon.The doped epitaxial silicon may include at least one of carbon,germanium, phosphorus, arsenic or boron.

Referring to FIG. 5, another method for selective epitaxial growth isillustratively shown, which employs, e.g., an RF or DC plasma enhancedchemical vapor deposition process. In block 502, a crystalline substratematerial is provided. The substrate material may include Si, Ge, III-Vmaterials, etc. In block 504, an oxide or insulator is grown on thesubstrate material. In block 506, the insulator (e.g., oxide) is openedup or patterned to form exposed areas of the substrate material.

In block 512, silicon is deposited on the exposed areas of the substratematerial to form epitaxial silicon on the exposed areas and formnon-epitaxial silicon in other than the exposed areas in a lowtemperature process (e.g., deposition temperature less than 500 degreesCelsius, and more preferably less than 250 degrees Celsius). In block514, silicon deposition includes diluting a source gas with a dilutiongas including at least one of H₂, HCl, Cl₂ and Ar with a gas ratio ofdilution gas to source gas of less than 1000, wherein the source gasincludes one of SiH₄, dichlorosilane (DCS), SiF₄ or SiCl₄.

In block 516, the non-epitaxial (e.g., amorphous or polysilicon) siliconis selectively etched using a plasma, and further epitaxial depositionof silicon is performed over the exposed areas. The plasma may includeat least one of H₂, HCl, Cl₂ or Ar.

In block 518, a dopant species or multiple dopant species may beintroduced with a gas ratio which provides a doped epitaxial silicon.The doped epitaxial silicon may include at least one of carbon,germanium, phosphorus, arsenic or boron. In block 520, selectiveepitaxial growth is provided by alternating the depositing and etchingsteps, or the depositing and etching are concurrently performed.

Having described preferred embodiments for ultra low-temperatureselective epitaxial growth of silicon for device integration (which areintended to be illustrative and not limiting), it is noted thatmodifications and variations can be made by persons skilled in the artin light of the above teachings. It is therefore to be understood thatchanges may be made in the particular embodiments disclosed which arewithin the scope of the invention as outlined by the appended claims.Having thus described aspects of the invention, with the details andparticularity required by the patent laws, what is claimed and desiredprotected by Letters Patent is set forth in the appended claims.

What is claimed is:
 1. An epitaxy method, comprising: providing acrystalline substrate material; growing an insulator on the substratematerial; opening the insulator to form exposed areas of the substratematerial; depositing silicon on the exposed areas of the substratematerial to form epitaxial silicon on the exposed areas and formnon-epitaxial silicon in other than the exposed areas in a lowtemperature process wherein a deposition temperature is less than 500degrees Celsius; and etching the non-epitaxial silicon using a plasma tofurther epitaxial deposition of silicon over the exposed areas, whereinthe steps of depositing and etching are concurrently performed.
 2. Themethod as recited in claim 1, wherein depositing silicon includes aradio frequency or direct current plasma enhanced chemical vapordeposition process.
 3. The method as recited in claim 1, whereindepositing silicon includes diluting a source gas with a dilution gasincluding at least one of H₂, HCl, Cl₂ and Ar with a gas ratio ofdilution gas to source gas of less than 1000, wherein the source gasincludes one of SiH₄, dichlorosilane (DCS), SiF₄ or SiCl₄.
 4. The methodas recited in claim 3, wherein diluting include diluting SiH₄ with atleast one of H₂ with a gas ratio of over
 5. 5. The method as recited inclaim 1, wherein the deposition temperature is less than 250 degreesCelsius.
 6. The method as recited in claim 1, wherein the substratematerial includes one of Si, Ge, and III-V materials.
 7. The method asrecited in claim 1, further comprising introducing a dopant with a gasratio which provides a doped epitaxial silicon.
 8. The method as recitedin claim 7, wherein the doped epitaxial silicon includes at least one ofcarbon, germanium, phosphorus, arsenic or boron.
 9. The method asrecited in claim 1, wherein the plasma includes at least one of H₂, HCl,Cl₂ or Ar.
 10. An epitaxy method, comprising: providing a crystallinesubstrate material; growing an insulator on the substrate material;opening the insulator to form exposed areas of the substrate material;and depositing silicon on the exposed areas of the substrate material toform epitaxial silicon on the exposed areas areas in a low temperatureprocess wherein a deposition temperature is less than 500 degreesCelsius concurrently with etching non-epitaxial silicon using a plasma.11. The method as recited in claim 10, wherein depositing siliconincludes a radio frequency or direct current plasma enhanced chemicalvapor deposition process.
 12. The method as recited in claim 10, whereindepositing silicon includes diluting a source gas with a dilution gasincluding at least one of H₂, HCl, Cl₂ and Ar with a gas ratio ofdilution gas to source gas of less than 1000, wherein the source gasincludes one of SiH₄, dichlorosilane (DCS), SiF₄ or SiCl₄.
 13. Themethod as recited in claim 12, wherein diluting include diluting SiH₄with at least one of H₂ with a gas ratio of over
 5. 14. The method asrecited in claim 10, wherein the deposition temperature is less than 250degrees Celsius.
 15. The method as recited in claim 10, wherein thesubstrate material includes one of Si, Ge, and III-V materials.
 16. Themethod as recited in claim 10, further comprising introducing a dopantwith a gas ratio which provides a doped epitaxial silicon.
 17. Themethod as recited in claim 16, wherein the doped epitaxial siliconincludes at least one of carbon, germanium, phosphorus, arsenic orboron.
 18. The method as recited in claim 10, wherein the plasmaincludes at least one of H₂, HCl, Cl₂ or Ar.
 19. An epitaxy method,comprising: forming an insulator having an opening exposing a portion ofan underlying crystalline material; depositing silicon on the exposedareas of the crystalline material to form epitaxial silicon on theexposed areas and form non-epitaxial silicon in other than the exposedareas in a low temperature process wherein a deposition temperature isless than 500 degrees Celsius; and etching the non-epitaxial siliconusing a plasma to further epitaxial deposition of silicon over theexposed areas, wherein the steps of depositing and etching areconcurrently performed.
 20. The epitaxy method of claim 19, wherein theplasma includes at least one of H₂, HCl, Cl₂ or Ar.